? semiconductor components industries, llc, 2013 may, 2013 ? rev. 9 1 publication order number: MC14514B/d MC14514B, mc14515b 4-bit transparent latch / 4-to-16 line decoder the MC14514B and mc14515b are two output options of a 4 to 16 line decoder with latched inputs. the MC14514B (output active high option) presents a logical ?1? at the selected output, whereas the mc14515b (output active low option) presents a logical ?0? at the selected output. the latches are r ? s type flip ? flops which hold the last input data presented prior to the strobe transition from ?1? to ?0?. these high and low options of a 4 ? bit latch / 4 to 16 line decoder are constructed with n ? channel and p ? channel enhancement mode devices in a single monolithic structure. the latches are r ? s type flip ? flops and data is admitted upon a signal incident at the strobe input, decoded, and presented at the output. these complementary circuits find primary use in decoding applications where low power dissipation and/or high noise immunity is desired. features ? supply voltage range = 3.0 vdc to 18 vdc ? capable of driving two low ? power ttl loads or one low ? power schottky ttl load the rated temperature range ? these devices are pb ? free and are rohs compliant ? nlv prefix for automotive and other applications requiring unique site and control change requirements; aec ? q100 qualified and ppap capable maximum ratings (voltages referenced to v ss ) parameter symbol value unit dc supply voltage range v dd ? 0.5 to +18.0 v input or output voltage range (dc or transient) v in , v out ? 0.5 to v dd +0.5 v input or output current (dc or transient) per pin i in , i out 10 ma power dissipation per package (note 1) p d 500 mw ambient temperature range t a ? 55 to +125 c storage temperature range t stg ? 65 to +150 c lead temperature (8 ? second soldering) t l 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. 1. temperature derating: plastic ?p and d/dw? packages: ? 7.0 mw/ c from 65 c to 125 c this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high ? impedance circuit. for proper operation, v in and v out should be constrained to the range v ss (v in or v out ) v dd . unused inputs must always be tied to an appropriate logic voltage level (e.g., either v ss or v dd ). unused outputs must be left open. xx = 14 or 15 a = assembly location wl = wafer lot yy = year ww = work week g = pb ? free package marking diagram 1 24 soic ? 24 dw suffix case 751e 145xxb awlyywwg see detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. ordering information http://onsemi.com s5 s7 d2 d1 st s3 s4 s6 s10 d3 d4 inh v dd s15 s14 s9 5 4 3 2 1 10 9 8 7 6 14 15 16 17 18 19 20 13 11 12 21 22 23 24 s13 s12 s8 s11 s0 v ss s2 s1 pin assignment
MC14514B, mc14515b http://onsemi.com 2 data inputs selected output mc14514 = logic ?1? inhibit d c b a mc14515 = logic ?0? 00000 s0 00001 s1 00010 s2 00011 s3 00100 s4 00101 s5 00110 s6 00111 s7 01000 s8 01001 s9 0 1 0 1 0 s10 01011 s11 0 1 1 0 0 s12 0 1 1 0 1 s13 0 1 1 1 0 s14 0 1 1 1 1 s15 1 x x x x all outputs = 0, mc14514 all outputs = 1, mc14515 decode truth table (strobe = 1)* x = don?t care *strobe = 0, data is latched block diagram v dd = pin 24 v ss = pin 12 4 to 16 decoder transparent latch strobe inhibit 2 3 1 21 22 23 data 1 data 2 data 3 data 4 a b c d20 17 18 4 5 6 7 8 10 9 11 19 16 13 14 15 a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d a b c d s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 ordering information device package shipping ? MC14514Bdwr2g soic ? 24 (pb ? free) 1000 / tape & reel nlv14514bdwr2g* mc14515bdwr2g soic ? 24 (pb ? free) 1000 / tape & reel nlv14515bdwr2g* ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *nlv prefix for automotive and other applications requiring unique site and control change requirements; aec ? q100 qualified and ppap capable.
MC14514B, mc14515b http://onsemi.com 3 ????????????????????????????????? ????????????????????????????????? (voltages referenced to v ss ) characteristic symbol v dd vdc ? 55 c 25 c 125 c unit min max min typ (note 2) max min max output voltage ?0? level v in = v dd or 0 ?1? level v in = 0 or v dd v ol 5.0 10 15 ? ? ? 0.05 0.05 0.05 ? ? ? 0 0 0 0.05 0.05 0.05 ? ? ? 0.05 0.05 0.05 vdc v oh 5.0 10 15 4.95 9.95 14.95 ? ? ? 4.95 9.95 14.95 5.0 10 15 ? ? ? 4.95 9.95 14.95 ? ? ? vdc input voltage ?0? level (v o = 4.5 or 0.5 vdc) (v o = 9.0 or 1.0 vdc) (v o = 13.5 or 1.5 vdc) ?1? level (v o = 0.5 or 4.5 vdc) (v o = 1.0 or 9.0 vdc) (v o = 1.5 or 13.5 vdc) v il 5.0 10 15 ? ? ? 1.5 3.0 4.0 ? ? ? 2.25 4.50 6.75 1.5 3.0 4.0 ? ? ? 1.5 3.0 4.0 vdc v ih 5.0 10 15 3.5 7.0 11 ? ? ? 3.5 7.0 11 2.75 5.50 8.25 ? ? ? 3.5 7.0 11 ? ? ? vdc output drive current (v oh = 2.5 vdc) source (v oh = 4.6 vdc) (v oh = 9.5 vdc) (v oh = 13.5 vdc) (v ol = 0.4 vdc) sink (v ol = 0.5 vdc) (v ol = 1.5 vdc) i oh 5.0 5.0 10 15 ? 1.2 ? 0.25 ? 0.62 ? 1.8 ? ? ? ? ? 1.0 ? 0.2 ? 0.5 ? 1.5 ? 1.7 ? 0.36 ? 0.9 ? 3.5 ? ? ? ? ? 0.7 ? 0.14 ? 0.35 ? 1.1 ? ? ? ? madc i ol 5.0 10 15 0.64 1.6 4.2 ? ? ? 0.51 1.3 3.4 0.88 2.25 8.8 ? ? ? 0.36 0.9 2.4 ? ? ? madc input current i in 15 ? 0.1 ? 0.00001 0.1 ? 1.0 adc input capacitance (v in = 0) c in ? ? ? ? 5.0 7.5 ? ? pf quiescent current (per package) i dd 5.0 10 15 ? ? ? 5.0 10 20 ? ? ? 0.005 0.010 0.015 5.0 10 20 ? ? ? 150 300 600 adc total supply current (note 3, 4) (dynamic plus quiescent, per package) (c l = 50 pf on all outputs, all buffers switching) i tl 5.0 10 15 i t = (1.35 a/khz) f + i dd i t = (2.70 a/khz) f + i dd i t = (4.05 a/khz) f + i dd adc 2. data labelled ?typ? is not to be used for design purposes but is intended as an indication of the ic?s potential performance. 3. the formulas given are for the typical characteristics only at 25 c. 4. to calculate total supply current at loads other than 50 pf: i t (c l ) = i t (50 pf) + (c l ? 50) vfk where: i t is in a (per package), c l in pf, v = (v dd ? v ss ) in volts, f in khz is input frequency, and k = 0.002.
MC14514B, mc14515b http://onsemi.com 4 ????????????????????????????????? ????????????????????????????????? (note 5) (c l = 50 pf, t a = 25 c) characteristic symbol v dd all types unit min typ (note 6) max output rise time t tlh = (3.0 ns/pf) c l + 30 ns t tlh = (1.5 ns/pf) c l + 15 ns t tlh = (1.1 ns/pf) c l + 10 ns t tlh 5.0 10 15 ? ? ? 180 90 65 360 180 130 ns output fall time t thl = (1.5 ns/pf) c l + 25 ns t thl = (0.75 ns/pf) c l + 12.5 ns t thl = (0.55 ns/pf) c l + 9.5 ns t thl 5.0 10 15 ? ? ? 100 50 40 200 100 80 ns propagation delay time; data, strobe to s t plh , t phl = (1.7 ns/pf) c l + 465 ns t plh , t phl = (0.86 ns/pf) c l + 192 ns t plh , t phl = (0.5 ns/pf) c l + 125 ns t plh , t phl 5.0 10 15 ? ? ? 550 225 150 1100 450 300 ns inhibit propagation delay times t plh , t phl = (1.7 ns/pf) c l + 315 ns t plh , t phl = (0.66 ns/pf) c l + 117 ns t plh , t phl = (0.5 ns/pf) c l + 75 ns t plh , t phl 5.0 10 15 ? ? ? 400 150 100 800 300 200 ns setup time data to strobe t su 5.0 10 15 250 100 75 125 50 38 ? ? ? ns hold time strobe to data t h 5.0 10 15 ? 20 0 10 ? 100 ? 40 ? 30 ? ? ? ns strobe pulse width t wh 5.0 10 15 350 100 75 175 50 38 ? ? ? ns 5. the formulas given are for the typical characteristics only at 25 c. 6. data labelled ?typ? is not to be used for design purposes but is intended as an indication of the ic?s potential performance. figure 1. drain characteristics test circuit external power supply v ss strobe inhibit d1 d2 d3 d4 v dd v ds i d for mc14515b 1. for p ? channel: inhibit = v dd 2. for n ? channel: inhibit = v ss 2. and d1 ? d4 constitute binary 2. code for ?output under test.? for MC14514B 1. for p ? channel: inhibit = v ss 1. and d1 ? d4 constitute 1. binary code for ?output 1. under test.? 2. for n ? channel: inhibit = v dd s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0
MC14514B, mc14515b http://onsemi.com 5 figure 2. dynamic power dissipation test circuit and waveform pulse generator c l c l v dd v dd v ss s0 s15 12 24 i d 0.01 f ceramic 500 f v dd v ss v in 20 ns 20 ns 90% 10% strobe d1 d2 d3 d4 inhibit figure 3. switching time test circuit and waveforms programmable pulse generator v dd strobe inhibit d1 d2 d3 d4 c l v dd v ss v dd v ss s0 s1 s15 v ss c l c l input output t tlh t tlh t thl t thl t phl t plh 20 ns output s0 output s1 output s15 90% 50% 10% 90% 50% 10%
MC14514B, mc14515b http://onsemi.com 6 logic diagram data 1 2 data 2 3 data 3 21 data 4 22 strobe 1 inhibit 23 q q r s q q r s q q r s q q r s a b c d in mc14515b only a b c d 11 s0 9s1 10 s2 8s3 7s4 6s5 5s6 4s7 18 s8 17 s9 20 s10 19 s11 14 s12 13 s13 16 s14 15 s15 ab c d a bc d ab c d a b cd ab cd a bcd ab cd a b c d ab c d a bc d ab c d a b cd ab cd a bcd ab cd
MC14514B, mc14515b http://onsemi.com 7 complex data routing two mc14512 eight ? channel data selectors are used here with the MC14514B four ? bit latch/decoder to effect a complex data routing system. a total of 16 inputs from data registers are selected and transferred via a 3 ? state data bus to a data distributor for rearrangement and entry into 16 output registers. in this way sequential data can be re ? routed or intermixed according to patterns determined by data select and distribution inputs. data is placed into the routing scheme via the eight inputs on both mc14512 data selectors. one register is assigned to each input. the signals on a0, a1, and a2 choose one of eight inputs for transfer out to the 3 ? state data bus. a fourth signal, labelled dis, disables one of the mc14512 selectors, assuring transfer of data from only one register. in addition to a choice of input registers, 1 thru 16, the rate of transfer of the sequential information can also be varied. that is, if the mc14512 were addressed at a rate that is eight times faster then the shift frequency of the input registers, the most significant bit (msb) from each register could be selected for transfer to the data bus. therefore, all of the most significant bits from all of the registers can be transferred to the data bus before the next most significant bit is presented for transfer by the input registers. information from the 3 ? state bus is redistributed by the MC14514B four ? bit latch/decoder. using the four ? bit address, d1 thru d4, the information on the inhibit line can be transferred to the addressed output line to the desired output registers, a thru p. this distribution of data bits to the output registers can be made in many complex patterns. for example, all of the most significant bits from the input registers can be routed into output register a, all of the next most significant bits into register b, etc. in this way horizontal, vertical, or other methods of data slicing can be implemented. data routing system input registers data transfer data distribution output registers 3-state data bus register a register p register 1 register 8 register 9 register 16 data select strobe inhibit dis dis q q d1 d2 d3 d4 a0 a1 a2 a0 a1 a2 MC14514B mc14512 mc14512 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0
MC14514B, mc14515b http://onsemi.com 8 package dimensions soic ? 24 wb case 751e ? 04 issue f b m 0.25 c seating plane a1 m l detail a end view h notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimensions b and c apply to the flat sec- tion of the lead and are measured between 0.10 and 0.25 from the lead tip. 4. dimensions d and e1 do not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 mm per side. interlead flash or protrusion shall not exceed 0.25 per side. dimensions d and e1 are determined at datum h. 5. a1 is defined as the vertical distance from the seating plane to the lowest point on the package body. note 3 pin 1 12 1 24 13 top view dim min max millimeters a 2.35 2.65 b 0.35 0.49 e 1.27 bsc h 0.25 0.75 c 0.23 0.32 a1 0.13 0.29 l 0.41 0.90 m 0 8 d e1 side view 11.00 24x 0.52 24x 1.62 1.27 dimensions: millimeters 1 pitch *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* e 10.30 bsc recommended indicator a b 0.25 c 24x b a c a note 5 x 45 c note 3 detail a c h d 15.25 15.54 e1 7.40 7.60 e s s e on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 MC14514B/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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